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| ELECTRONICS INC. 10/100 LAN Interface Module with Enhanced Common Mode Attenuation EPF8033GM * Optimized for DP83840A/DP83223 Chip Set * * Recommended for use with ICS 1890 Series and SS578Q2120 * when connected per appropriate schematic * Guaranteed to operate with 8 mA DC bias at 70C * * Complies with or exceeds IEEE 802.3, 10 BT/100 BX Standards * Electrical Parameters @ 25 C OCL @ 70C 100 KHz, 0.1 Vrms 8 mA DC Bias Cable Side 350H Insertion Loss (dB Max.) 1-80 MHz Xmit -1 Rcv -1 * 80-100 MHz Xmit -2 Rcv -2 1-30 MHz Return Loss (dB Min.) 30-60 MHz 60-100 MHz Common Mode Rejection (dB Min.) 1-30 MHz 30-100 MHz 100-500 MHz Crosstalk (dB Min.) [Between Channels] 5-10 MHz 10-100 MHz Xmit Rcv Xmit -18 -18 -12 Rcv Xmit -12 -10 Rcv Xmit Rcv Xmit Rcv Xmit Rcv -10 -40 -40 -35 -30 -8 -10 -38 -38 Isolation : 1500 Vrms * Impedance : 100 * Rise Time : 3.0 nS Max. * Schematic Receive Channel RD+ 1 7 RX+ CT 14 TD- 15 Transmit Channel 12 CT 11 TX- RD- 2 1:1 CT 3 6 RX5 CT TD+ 16 1:1 10 TX+ Package A J Pin 1 I.D. PCA EPF8033GM Date Code Pad Layout Dimensions N Dim. A B C D E F G H I J K L M N P Q Min. .970 .380 .234 --.010 --.460 .017 .008 --0 .025 --------(Inches) Max. Nom. .990 .400 .252 --.015 --.510 .022 .013 --8 .045 --------.980 .390 .247 .700 .013 .100 .500 .020 .011 .140 4 .035 .030 .100 .092 .560 (Millimeters) Min. Max. Nom. 24.64 9.65 5.94 --.254 --12.45 .432 .203 --0 .635 --------25.15 10.16 6.40 --.381 --12.95 .559 .330 --8 1.14 --------24.89 9.91 6.30 17.78 .330 2.54 12.70 .508 .279 3.56 4 .889 .762 2.54 2.34 14.22 B Q P D E M I L C K H F G PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 CSF8033GMa Rev. 2 2/27/01 Product performance is limited to specified parameters. Data is subject to change without prior notice. TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com ELECTRONICS INC. 10/100 LAN Interface Module with Enhanced Common Mode Attenuation The circuit below is a guideline for interconnecting PCA's EPF8033GM with National DP83840A and DP83223 twister chip set for 10/100 Mb/s applications. Further details can be obtained from the chip manufacturer application notes. Please consult PCA for applications help regarding the SSI78Q2120 or ICS1890 series parts or consult with the respective application notes. Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded signals in 10/100 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust the TXREF resistor of the twister chip to get at least 2.12V pk-pk across pins 16-15. Note that significant low frequency response improvement can be obtained in the system (improving equalization effects) if the DC blocking capacitors were not used; this can only be done by choosing a different pinout for the 10 Base-T receiver side. This is accomplished without impacting any other behavior. If any user has a need to improve this feature, please consult with the PCA Technical support group . This solution is similar to approaches used in EPF8013GM, EPF8022G and EPF8038S (a repeater interface module). It is recommended that system designers do not use the receiver side center tap to ground, via a capacitor. This may worsen EMI, specifically if the secondary "common mode termination" is pulled to chassis ground as shown. The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is finalized. The "common mode termination" load of 75 shown from the center taps of the secondary may be taken to chassis ground via a cap of suitable value. This depends upon user's design, EMI margin etc. It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit the plane off at least 0.05 inches away from the chip side pins of EPF8033GM. There need not be any ground plane beyond this point. For best results, PCB designer should design the outgoing traces preferably to be 50 , balanced and well coupled to achieve minimum radiation from these traces. Typical Application Circuit for UTP (Excerpts from NSC DP83840A application notes) 0.10F {Note 1} + 1 7 75 50 8 7 6 5 4 75 RXD 1000pF 12.1 12.1 1000pF + 0.1F {Note 1} 5 2 16 15 14 12.1 12.1 6 50 + 10 12 11 2000V RJ45* TXU 3 2 1 TXO PMRD TD - EPF8033GM Isolation Cap RXI DP83840A DP83223 SD PMID Chassis Ground + SD + Other pull down/up resistors not shown, for clarification please refer to National's application notes. Notes : 1. See text above for clarification. 2. *NIC Side is shown. Hub side connections will have crossover swapping pins 3-6 & 1-2. RD - PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 CSF8033GMb Rev. 2 2/27/01 TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com |
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